All tasks from 4 exam sheets (Sheet 1 · Sheet 2 in two numerical variants · Sheet 3 · exam 22.06.2026) and the supplementary problem set. Each task includes the original question, a full worked solution, and an illustration where required by the instructor. Duplicates counted and solved only once.
Wrocław University of Science & Technology
Medical Informatics · English track
Compiled for exam prep
Static vs. incremental diode resistance — 2× (task 2 on both variants of Sheet 2) → task 5.2
Inverting amplifier 18 kΩ / 1 kΩ / 10 mV / 2 kΩ — 2× (task 4 on both variants of Sheet 2) → task 3.6
Gates NOT→AND→NOT (Y = X1 + X2) — 2× (task 5 on both variants of Sheet 2) → task 1.2
Total: 6 tasks appear exactly twice — each solved here only once. Several other tasks are variants of the same type with different numbers (e.g. diode protection 10 V/30 V vs 12 V/40 V, two UCE transistor values, three instrumentation amp versions, two slew rate versions) — these are NOT duplicates; each is solved separately and marked VARIANT.
1Digital Circuits — Logic Gates
IEC symbols as on the exam sheets: box "1" with bubble = NOT, "&" = AND, "=1" = XOR. Method: write the logic equation, simplify with De Morgan's law, produce the truth table.
1.1 · NOT + NOT → AND → NOT (OR function)
Sheet 1, task 5
Please determine responses that will appear on the Y output of the following digital system for all possible state combinations on the X1 and X2 inputs.
Circuit equationY = X1 · X2
Simplify (De Morgan's law)Y = X1 + X2 — negation of a product of negations equals the logical sum.
X1
X2
X1
X2
X1·X2
Y
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
0
1
ResultY = X1 OR X2 — the network implements logical OR.
Please determine responses that will appear on the Y output of the following digital system for all possible state combinations on the X1 and X2 inputs.
Circuit equationY = X1 · X2
Simplify (De Morgan's law)Y = X1 + X2
X1
X2
X1
X1·X2
Y
0
0
1
0
1
0
1
1
1
0
1
0
0
0
1
1
1
0
0
1
ResultY = X1 + X2 (Y = 0 only when X1 = 0 and X2 = 1).
Correction: the colleague's file electronics_exam_prep.html labels this circuit a plain NAND — that is incorrect. On the exam sheet X1 passes through a NOT gate first, giving Y = X1 + X2, as shown above.
Please determine responses that will appear on the Y output of the following digital system for all possible state combinations on the X1 and X2 inputs.
Circuit equationY = X1 ⊕ X2
Simplify
Inverting one XOR input negates the output: X1 ⊕ X2 = X1 ⊕ X2; the final NOT gate cancels it: Y = X1 ⊕ X2.
Sensor as voltage source → voltage divider → amplifier Rin must be HIGH. Sensor as current source → current divider → amplifier Rin must be LOW.
2.1 · Voltage source, Rsource = 500 Ω, ≥ 95%
Sheet 3, task 1DUPLICATE ×2
To an amplifier input a sensor is going to be connected, the output of which behaves like a voltage source with emf Esource and internal series resistance Rsource = 500 Ω. What input resistance should the amplifier have so that at least 95% of the emf Esource affects the amplifier input?
voltage divider: U_in = E · R_in / (R_in + R_source)
A sensor is connected to the input of an amplifier. The sensor's output behaves as a voltage source with an electromotive force Es and an internal series resistance Rs = 100 Ω. What input resistance Ri,ampl should the amplifier have so that at least 98% of the emf Es appears across the amplifier input?
A sensor, the output of which behaves like a current source, is going to be connected to the amplifier input. The current forced by the sensor equals Isource and its internal parallel resistance is Rsource = 100 kΩ. What input resistance should the amplifier have so that at least 95% of the Isource current flows into the amplifier input?
Gain from RMS/amplitude values, instrumentation amp output (CMRR error budget), inverting amplifier with source resistance, slew rate, gain-bandwidth product, closed-loop output resistance, precision op-amp parameter ranges.
3.1 · Voltage gain: input 20 mV (RMS), output 2.00 V (amplitude)
Sheet 1, task 3
When a sine wave signal of some frequency and with an effective value of 20 mV is applied to the input of the amplification circuit, a sine waveform with an amplitude of 2.00 V is observed at its output. What is the voltage gain of this amplifier at this frequency? Please justify your answer.
Key: compare like quantities
Input is given as RMS, output as amplitude — convert to the same domain:
Uin,m = Uin,RMS · √2 = 20 mV × 1.414 = 28.28 mV
Gain (amplitude / amplitude)ku = Uout,mUin,m = 2.00 V0.02828 V ≈ 70.7 V/V
3.2 · Voltage gain in dB: input 20 mV (amplitude), output 1.00 V (RMS)
Exam 22.06.2026, task 2VARIANT of task 3.1
When a sinusoidal signal of a given frequency and an amplitude of 20 mV is applied to the input of an amplifier circuit, a sinusoidal waveform with an RMS (effective) value of 1.00 V is observed at the output. What is the voltage gain of the amplifier in decibels (dB) at this frequency? Justify your answer.
Convert to the same domain (RMS)Uin,RMS = 20 mV√2 = 14.14 mV
Linear gainku = 1.00 V0.01414 V ≈ 70.7 V/V
Convert to decibelsku[dB] = 20·log10(70.7) ≈ 20 × 1.85 ≈ 37 dB
3.3 · Instrumentation amplifier: 1 mV / 20 V / CMRR = 100 dB
Sheet 1, task 4
A DC differential voltage of Uwe d = 1 mV superimposed on a common mode component Uwe cm = 20 V should be amplified. Both components have the same sign. An instrumentation amplifier was used that has a differential gain kud = 1000 V/V and CMRR = 100 dB. What voltage will appear at the output of this amplifier? Please assume that offset of this amplifier is negligible.
3.4 · Instrumentation amplifier: 1 mV / 10 V / CMRR = 120 dB
Problem set, task GVARIANT of task 3.3
The differential voltage of Uwe d = 1 mV superimposed on a common mode component Uwe cm = 10 V should be amplified. Both components have the same sign. An instrumentation amplifier was used that has a differential gain kud = 1000 V/V and CMRR = 120 dB. What voltage will appear at the output of this amplifier? Please assume that offset of this amplifier is negligible.
CMRR to linear & common-mode gainCMRR = 10120/20 = 106kucm = 1000106 = 0.001 V/V
SuperpositionUout = 1000×0.001 V + 0.001×10 V = 1 V + 0.01 V
3.5 · Instrumentation amplifier: 2 mV / 10 V / CMRR = 80 dB + adequacy check
Exam 22.06.2026, task 4VARIANT of task 3.3
A DC differential voltage of Uin,d = 2 mV, superimposed on a common-mode interference voltage of Uin,cm = 10 V, is to be amplified. Both components have the same polarity. An instrumentation amplifier with a differential gain of kud = 1000 V/V and a CMRR = 80 dB is used. What voltage will appear at the output of this amplifier? Can the CMRR of this amplifier be considered sufficient in this case? Assume that the amplifier's offset voltage is negligible.
CMRR to linear & common-mode gainCMRR = 1080/20 = 104kucm = 1000104 = 0.1 V/V
SuperpositionUout = 1000×0.002 V + 0.1×10 V = 2 V + 1 V = 3 V
Assessment of CMRR adequacy
The useful signal at the output is 2 V while the common-mode error is 1 V — 50% of the useful signal. CMRR = 80 dB is clearly insufficient. For a ≤ 1% error we need kucm·10 V ≤ 0.02 V, i.e. CMRR ≥ 1000×10/0.02 = 5×10⁵ ≈ 114 dB (in practice ≥ 120 dB).
ResultUout = 3 V (2 V signal + 1 V error). CMRR = 80 dB is NOT sufficient (50% error); need ≥ ~114–120 dB.
An inverting amplifier was built, in which RF = 18 kΩ and R1 = 1 kΩ. The input of this amplifier is connected to a DC voltage source with electromotive force Esource = 10 mV and internal series resistance Rsource = 2 kΩ. What voltage will appear at the output of this amplifier? Please assume that the amplifier is powered by two ±VCC symmetrical voltages.
R_source is in series with R₁ → effective input branch resistance = R₁ + R_source
An inverting amplifier was built, in which RF = 10 kΩ and R1 = 1 kΩ. The input of this amplifier is connected to a DC voltage source with electromotive force Esource = +10 mV and internal series resistance Rsource = 1 kΩ. What voltage will appear at the output of this amplifier? Please assume that the amplifier is powered by two ±VCC symmetrical voltages.
For a certain operational amplifier, the gain and bandwidth product is GBW = 1 MHz. What value of the upper limit frequency will be obtained for small signals if we use this operational amplifier to build a non-inverting amplifier in which the resistances in the negative feedback circuit are: RF = 9 kΩ and R1 = 1 kΩ?
3.11 · Closed-loop output resistance of a non-inverting amplifier
Problem set, task I
Please evaluate the output resistance of a non-inverting amplifier with gain of kuf = 100 V/V built using an operational amplifier with negative voltage feedback. The open loop parameters of the operational amplifier are: kud > 10⁵, and output resistance Routput ≈ 50 Ω.
3.13 · Comparison of IIB: bipolar vs. FET input stage
Problem set, task D
Please compare the IIB values and their temperature dependence for operational amplifiers whose input stage is built using bipolar transistors with amplifiers whose input stage is built using FETs.
Bipolar input stage (BJT): IIB is the base current of the input transistors — relatively large (nA – µA). Temperature dependence is weak: as T rises, β increases, so the base current at a given collector current actually decreases slightly.
FET input stage (JFET/MOSFET): IIB is the reverse-biased gate-junction leakage — very small (fA – pA), but increases exponentially with temperature: approximately doubles every ~10 °C. At elevated temperatures it may approach bipolar values in absolute terms.
ResultBJT: IIB large (nA–µA), weak T-dependence. FET: IIB very small (fA–pA), but ~×2 per 10 °C.
Base current from hFE and operating-point UCE from KVL (two numerical variants of the same circuit).
4.1 · Base current estimate from hFE
Sheet 1, task 2
According to the data sheet, the current gain hFE of the n-p-n bipolar transistor at UCE = 5 V and IC = 2 mA is hFE > 100. Please estimate the base current value needed for this.
Current gain definitionhFE = ICIB ⇒ IB = IChFE
Boundary estimate (hFE = 100)IB < 2 mA100 = 20 µA — since hFE > 100, the actual IB is smaller than this bound.
The emitter of the n-p-n bipolar transistor is connected to a negative terminal of the power supply. The transistor collector is connected to one of the terminals of the resistor RC = 4 kΩ. The other terminal of this resistor is connected to the positive terminal of the voltage source UCC = +10 V. What is the value of the UCE voltage if the transistor base is controlled so that the collector current IC = 1 mA? Please justify your answer.
emitter at ground (negative rail), R_C between collector and +U_CC
The emitter of the n-p-n bipolar transistor is connected to the negative terminal of the power supply. The collector is connected to one terminal of the resistor RC = 5 kΩ, while the other terminal of the resistor is connected to the positive terminal of the power source UCC = +15 V. What will the voltage UCE be if the transistor base is controlled such that the collector current IC = 2 mA? Please justify your answer.
KVL (same method as task 4.2)UCE = UCC − IC·RC = 15 V − 2 mA × 5 kΩ = 15 V − 10 V
Half-wave rectifier ripple, Zener diode safe current range, static vs. incremental resistance (graph required by the instructor!), input over-voltage protection (2 numerical variants), LED current-limiting resistor.
5.1 · Ripple period of a half-wave rectifier (Poland grid)
Sheet 1, task 1
Let us consider a power supplier circuit including a transformer, a half-wave rectifier and a ripple smoothing capacitor. What value the ripple period has at the output of such a supplier if it is connected to a power grid in Poland? Please justify your answer.
half-wave rectifier: capacitor recharged once per grid period (only one half-cycle conducts)
Justification
In a half-wave rectifier the capacitor is recharged only once per full grid period — only one half-cycle conducts. The ripple period therefore equals the grid period. Grid frequency in Poland: f = 50 Hz.
CalculationTripple = Tgrid = 1f = 150 Hz = 0.02 s = 20 ms
ResultT = 20 ms (for comparison: full-wave rectifier gives T = 10 ms)
5.2 · Static Rs vs. incremental (dynamic) Rd resistance of a forward-biased diode
Sheet 2, task 2DUPLICATE ×2
Which of the resistances of a forward-biased diode is greater: a static resistance Rs or an incremental (dynamic) Rd one, if the voltage across the diode is UF ≥ 0.6 V? Please provide the relevant definitions and a graphical justification to support your answer.
graph required by the instructor: secant (R_s) vs. tangent (R_d) on the diode I(U) characteristic
DefinitionsRs = UFIF (secant from origin to operating point)
Rd = dUFdIF ≈ VTIF (tangent at the operating point)
Comparison
The diode characteristic is exponential — the tangent at the operating point is far steeper than the secant, so Rd ≪ Rs. Quantitatively:
RsRd ≈ UFVT ≈ 0.6 V0.026 V ≈ 23 ≫ 1
ResultStatic resistance Rs is much greater than incremental resistance Rd.
5.3 · Zener diode 10 V / 0.5 W — safe current range
Sheet 3, task 3DUPLICATE ×2
The voltage stabilizer consisting of the Zener diode and the resistor uses a Zener diode with a nominal voltage of 10 V and a maximum DC power of 0.5 W. What maximum and minimum value can the diode current take so that the diode correctly and safely stabilizes the voltage? Please justify your answer.
parametric stabilizer: Zener diode operates in reverse breakdown
Maximum current — power limitIZ,max = PmaxUZ = 0.5 W10 V = 50 mA
Minimum current — regulation condition
The diode only stabilizes when biased past the Zener knee — current must not drop to zero. A practical minimum holding current is approximately 5–10% of Imax:
IZ,min ≈ 0.1 × 50 mA = 5 mA
ResultIZ,max = 50 mA; IZ,min ≈ 5 mA (must keep the diode past the breakdown knee)
5.4 · Input protection: limit 10 V, external up to 30 V, IF,max = 20 mA
Sheet 2 (variant A), task 1
Input of the DC amplifier is protected against excessive voltage by a diode and a resistor. A diode is used for which maximum DC forward current equals IF max = 20 mA. What value should the diode's cathode potential have so that the voltage at the protected amplifier input does not exceed 10 V? Please select the value of the additional resistor Rg so that the external input constant voltage can be up to 30 V. Please assume that the current absorbed by the protected amplifier input is negligible. Please provide a justification of your answers.
diode begins conducting when node exceeds U_K — excess current flows through diode to the U_K reference
Cathode potential
The diode anode sits at the protected node; its cathode is tied to the UK reference. The node cannot exceed UK + UF. Assuming an ideal diode (UF ≈ 0): UK = 10 V. (For a real diode with UF ≈ 0.7 V, set UK ≈ 9.3 V.)
Series resistor — worst case (30 V in, node clamped at 10 V)
All current flows through the diode (amplifier input draws negligible current):
Rg ≥ Uin,max − UKIF,max = 30 V − 10 V20 mA = 1 kΩ
5.5 · Input protection: limit 12 V, external up to 40 V, IF,max = 20 mA
Sheet 2 (variant B), task 1VARIANT of task 5.4
The input of a DC amplifier is protected against excessive voltage by a diode and a resistor. A diode with a maximum DC forward current of IF max = 20 mA is used. What value should the diode's cathode potential have so that the voltage at the protected amplifier input does not exceed 12 V? Select the value of the additional resistor Rg so that the external DC input voltage can take values up to 40 V. Assume that the current absorbed by the protected amplifier input is negligible, and provide a justification for your answer.
Same method as task 5.4UK = 12 VRg ≥ 40 V − 12 V20 mA = 28 V0.02 A = 1.4 kΩ
5.6 · LED current-limiting resistor: 15 mA / 3.3 V / 15 V supply
Exam 22.06.2026, task 3
The LED provides sufficient brightness at a forward current of 15 mA, where the voltage drop across the diode is 3.3 V. Select a resistor that ensures the diode operates at this point when powered by an ideal voltage source with an electromotive force of 15.0 V.
KVL around the loopE = I·R + ULED ⇒ R = E − ULEDI
SubstituteR = 15.0 V − 3.3 V15 mA = 11.7 V0.015 A = 780 Ω